Title :
A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS
Author :
Frans, Yohan ; Nguyen, Nhat ; Daly, Barry ; Wang, Yueyong ; Kim, Dennis ; Bystrom, Todd ; Olarte, Dennis ; Donnelly, Kevin
Author_Institution :
Rambus Inc.,, Los Altos, CA, USA
Abstract :
A quad transceiver cell is designed and implemented in 90nm CMOS technology with a 1V nominal supply. To minimize area and power consumption, the cell uses a single dual-loop PLL. Gate-current leakage compensator is used to mitigate gate-current leakage in the PLL loop-filter capacitor. The quad cell consumes 73mW/link at 3.125Gbps with 500mV output swing driving double-terminated links and achieves a peak-to-peak transmit jitter of 42ps at 4Gbps data rate.
Keywords :
CMOS integrated circuits; jitter; leakage currents; phase locked loops; transceivers; 1 to 4 Gbit/s; 1-4 Gbps quad transceiver cell; 42 ps; 500 mV; 90 nm; 90nm CMOS; PLL; gate-current leakage compensator; jitter; power consumption; CMOS technology; Capacitors; Charge pumps; Clocks; Jitter; Phase frequency detector; Phase locked loops; Sampling methods; Signal generators; Transceivers;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346534
