Title :
The ballistic nano-transistor
Author :
Timp, G. ; Bude, J. ; Bourdelle, K.K. ; Garno, J. ; Ghetti, A. ; Gossmann, H. ; Green, M. ; Forsyth, G. ; Kim, Y. ; Kleiman, R. ; Klemens, F. ; Kornblit, A. ; Lochstampfor, C. ; Mansfield, W. ; Moccio, S. ; Sorsch, T. ; Tennant, D.M. ; Timp, W. ; Tung, R.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (<2 nm) gate oxides in sub-30 nm effective channel length nMOSFETs. The peak drive performance in an nMOSFET was observed at t/sub ox//spl ap/1.3 nm for a 1.5 V power supply voltage with T/sub n//spl ap/0.7, while the peak performance in a pMOSFET was observed at t/sub ox//spl ap/1.5 nm for a -1.5 V supply with T/sub p//spl ap/0.5. Since the carrier scattering in the channel is due predominately to interface roughness, reducing the transverse surface field, either by reducing the gate voltage or by increasing the oxide thickness, can be used to improve the transmittance T/sub n//spl rarr/0.85, T/sub p//spl rarr/0.6, while diminishing the drive current.
Keywords :
CMOS integrated circuits; MOSFET; interface roughness; nanotechnology; semiconductor device measurement; surface scattering; 1.3 to 2 nm; 1.5 V; 30 nm; CMOS technology; Si-SiO/sub 2/; ballistic nano-transistor; ballistic transport; carrier scattering; effective channel length; gate voltage; high drive current performance; interface roughness; nMOSFETs; oxide thickness; pMOSFET; peak drive performance; power supply voltage; transmittance; transverse surface field; ultra-thin gate oxides; Ballistic transport; CMOS technology; Etching; FETs; MOSFET circuits; Rough surfaces; Scattering; Silicon; Surface roughness; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.823845
