Title :
The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length
Author :
Hergenrother, J.M. ; Monroe, D. ; Klemens, F.P. ; Komblit, A. ; Weber, G.R. ; Mansfield, W.M. ; Baker, M.R. ; Baumann, F.H. ; Bolan, K.J. ; Bower, J.E. ; Ciampa, N.A. ; Cirelli, R.A. ; Colonell, J.I. ; Eaglesham, D.J. ; Frackoviak, J. ; Gossmann, H.J. ; G
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
We have fabricated and demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET. This is the first MOSFET ever built that combines (1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and (2) a high-quality gate oxide grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes a self-aligned S/D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S/D capacitances. The drive current per /spl mu/m of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel. All of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths (L/sub G/) have been demonstrated without advanced lithography.
Keywords :
MOSFET; capacitance; oxidation; scanning probe microscopy; semiconductor device measurement; 50 nm; Si-SiO/sub 2/; VRG-MOSFET; deposited film thickness; drive current; electrical performance; gate length control; high-quality gate oxide; junction capacitance; lithography-independent gate length; manufacturing methods; parasitic overlap capacitance; rectangular device pillar; scanning capacitance microscopy; single-crystal Si channel; solid source diffusion; source/drain capacitance; vertical replacement-gate MOSFET; Etching; Lithography; MOSFET circuits; Manufacturing; Parasitic capacitance; Reluctance generators; Semiconductor films; Solids; Thickness control; Transistors;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.823850
