Investigation of plasma-induced charging damage for nMOSFETs with conventional or damascene Al interconnects

Plasma-charging damage on nMOSFETs with conventional or damascene Al interconnects has been investigated. The high density plasma (HDP) CVD process for filling SiO/sub 2/ between narrow pitched metal lines gives serious damage on MOSFETs, resulting in increase of the gate leakage current and junction leakage (Ioff). In the case of damascene interconnect without the HDP-SiO/sub 2/ deposition process, no junction leakage is observed, and the chip yield is twice that using conventional interconnect. The damascene interconnect is the key for maintaining chip yield in deep sub-quarter-micron MOSFETs.