• DocumentCode
    1638449
  • Title

    A 2.8 Gb/s, 32-state, radix-4 Viterbi decoder add-compare-select unit

  • Author

    Bruels, Niko ; Sicheneder, Elisabeth ; Loew, Manuel ; Schackow, Alex ; Gliese, Joerg ; Sauer, Christian

  • Author_Institution
    Corporate Res., Infineon Technol.,, Munich, Germany
  • fYear
    2004
  • Firstpage
    170
  • Lastpage
    173
  • Abstract
    A 0.13 μm CMOS add-compare-select unit (ACSU) is presented allowing for a maximum data rate of 2.8 Gb/s. A modified bit-level pipelining scheme combined with a new state metric representation has been implemented using single-rail DOMINO logic and static CMOS gates. The adaptation of architecture and circuit technique results in a compact energy-efficient design. The 0.5mm2 chip consumes 970mW at 2 Gb/s (VDD = 1.2 V) and 2.2 W at 2.8 Gb/s (VDD = 1.5 V).
  • Keywords
    CMOS integrated circuits; VLSI; Viterbi decoding; 2.8 Gbit/s; modified bit-level pipelining scheme; radix-4 Viterbi decoder add-compare-select unit; single-rail DOMINO logic; static CMOS gates; CMOS digital integrated circuits; CMOS logic circuits; Convolutional codes; Costs; Decoding; Energy consumption; Packaging; Pipeline processing; Throughput; Viterbi algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8287-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2004.1346546
  • Filename
    1346546
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1638449