• DocumentCode
    1638459
  • Title

    A 64-state 2GHz 500Mbps 40mW Viterbi accelerator in 90nm CMOS

  • Author

    Anders, Mark ; Mathew, Sanu ; Krishnamurthy, Ram ; Borkar, Shekhar

  • Author_Institution
    Circuit Res. Lab., Intel Corp., Hillsboro, OR, USA
  • fYear
    2004
  • Firstpage
    174
  • Lastpage
    175
  • Abstract
    A 64-state Viterbi accelerator fabricated in 1.2V, 90nm dual-Vt CMOS technology is described for 2GHz operation and fastest reported 500Mbps data rate (1 Gbps decode for 1/2 rate codes). Novel radix-4 add-compare-select circuits and low-energy traceback register file techniques enable 40mW total power at 1.2V, 2GHz, and scalability to 5mW at 0.7V, 216MHz (for 802.11 a wireless baseband).
  • Keywords
    CMOS integrated circuits; Viterbi decoding; 2 GHz; 40 mW; 500 Mbit/s; 90 nm; 90nm CMOS; Viterbi accelerator; low-energy traceback register file techniques; radix-4 add-compare-select circuits; scalability; Adders; Baseband; CMOS technology; Circuits; Computer hacking; Maximum likelihood decoding; Registers; Routing; Scalability; Viterbi algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8287-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2004.1346547
  • Filename
    1346547
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1638459