Title :
A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture
Author :
Kuo, J.B. ; Liao, H.J. ; Chen, H.P.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
The authors present a BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers without race problems using a Wallace tree reduction architecture. With the BiCMOS dynamic full adder circuit, an 8×8 multiplier designed based on a 2-μm BiCMOS technology showed a 6x improvement in speed as compared to a CMOS static circuit
Keywords :
BiCMOS integrated circuits; VLSI; adders; digital arithmetic; integrated logic circuits; multiplying circuits; parallel processing; 2 micron; BiCMOS technology; VLSI implementation; Wallace tree reduction architecture; dynamic full adder circuit; high-speed parallel multipliers; Adders; BiCMOS integrated circuits; Buildings; CMOS technology; Clocks; Digital systems; Logic circuits; Logic gates; Switches; Very large scale integration;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-0727-5
DOI :
10.1109/BIPOL.1992.274053
