An area efficient multiplier using current-mode quaternary logic technique

This paper proposes an area efficient 8×8 bit multiplier using current-mode quaternary logic technique. The multiplier is functionally partitioned into the following major sections: current-mode CMOS binary-to-quaternary encoder, current-mode quaternary logic full-adder block, and current-mode quaternary-to-binary decoder. The proposed multiplier has 2.4ns of propagation delay and 3.0mW of power consumption. Also, this multiplier can be adapted to binary system by the encoder and the decoder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25um standard CMOS technology with the supply voltage 2.5V.