Title :
A 4.8-ns random access 144-Mb twin-cell-memory fabricated using 0.11-μm cost-effective DRAM technology
Author :
Noda, Hiromasa ; Miyatake, Shinichi ; Sekiguchi, Tomonori ; Takemura, Riichiro ; Sakata, Takeshi ; Saino, Kanta ; Kato, Yoshiki ; Kitamura, Eiji ; Kajigaya, Kazuhiko
Author_Institution :
Elpida Memory, Inc., Kanagawa, Japan
Abstract :
A 144-Mb twin-cell-memory was fabricated using 0.11-μm cost-effective DRAM technology. A direct-sense-amp with a three-stage sensing scheme can achieve a random access time of 4.8 ns. The source-separated restore-sense-amp enables a random cycle time of 6.0 ns. The peak bandwidth is 48 Gb/s with separate I/O and simultaneous read/write operations. High performance was also realized using W/WNx dual-gate CMOS technology with a p+ gate memory-cell-transistor.
Keywords :
CMOS integrated circuits; DRAM chips; 0.11 micron; 144 Mbit; 4.8 ns; 4.8-ns random access 144-Mb twin-cell-memory; 6.0 ns; DRAM; direct-sense-amp; dual-gate CMOS technology; peak bandwidth; random access time; random cycle time; simultaneous read/write operations; three-stage sensing scheme; Bandwidth; CMOS technology; Circuits; Laboratories; Memory architecture; Network servers; Random access memory; Research and development; Signal restoration; Ultra large scale integration;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346553
