Title :
A 50MS/s low-power 8-bit dynamic voltage comparator in 0.18μm CMOS process
Author_Institution :
ASIC Lab., Nat. Res. Nucl. Univ. MEPhI, Moscow, Russia
Abstract :
This paper describes a design technique for multi-stage high speed precision low-current consumption comparator utilizing charge-storage pre-amplifier. To reduce the average current consumption of the preamplifier capacitive dynamic load is used. To correct the offset voltage of pre-amplifier the OOS (Output Offset Storage) method is used. Presented technique is verified by design of 50 MS/s comparator in standard 0.18 μm CMOS process. Achieved power consumption of preamplifier is 18 μA, providing the input resolution less than 4 mV.
Keywords :
CMOS integrated circuits; current comparators; low-power electronics; preamplifiers; CMOS process; OOS method; average current consumption; charge-storage pre-amplifier; current 18 muA; low-current consumption comparator; low-power dynamic voltage comparator; output offset storage method; pre-amplifier capacitive dynamic load; size 0.18 mum; CMOS integrated circuits; CMOS process; Capacitance; Capacitors; Latches; Power demand; Transistors;
Conference_Titel :
Microelectronics Proceedings - MIEL 2014, 2014 29th International Conference on
Conference_Location :
Belgrade
Print_ISBN :
978-1-4799-5295-3
DOI :
10.1109/MIEL.2014.6842185
