High quality Ta/sub 2/O/sub 5/ gate dielectrics with T/sub ox.eq/<10 /spl Aring/

Author

Luan, H.F. ; Lee, S.J. ; Lee, C.H. ; Song, S.C. ; Mao, Y.L. ; Senzaki, Y. ; Roberts, D. ; Kwong, D.L.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

fYear

1999

Firstpage

141

Lastpage

144

Abstract

High quality Ta/sub 2/O/sub 5/ gate stack with T/sub ox,eq/=9 /spl Aring/ (measured @ Vg=-2.5 V in strong accumulation without taking quantum mechanical effects into account) and the leakage current Jg=0.19 A/cm/sup 2/ @ Vg=-1.0 V has been achieved using NH/sub 3/-based interface layer, H/sub 2//O/sub 2/ post-deposition anneal and TiN diffusion barrier. The leakage current of Ta/sub 2/O/sub 5/ gate stack with NO interface layer is 10/sup 4/x lower than that of RTP SiO/sub 2/ with same T/sub ox,eq/ and can be further reduced by a factor of 100 with NH/sub 3/-based interface layer.

Keywords

CMOS integrated circuits; CVD coatings; accumulation layers; annealing; dielectric thin films; leakage currents; tantalum compounds; -1.0 V; -2.5 V; CMOS technology; CVD films; Ta/sub 2/O/sub 5/; TiN; diffusion barrier; gate dielectrics; interface layer; leakage current; post-deposition anneal; strong accumulation; Annealing; CMOS technology; Capacitance-voltage characteristics; Electrodes; High K dielectric materials; High-K gate dielectrics; Hydrogen; Leakage current; Quantum mechanics; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823865

Filename

823865