Area-efficient low-power 8-bit 20-MS/s SAR ADC in 0.18μm CMOS

This paper presents the design results of the prototype IP block of the successive approximation analog-to-digital converter (SAR ADC) for implementation by 0.18 um MMRF CMOS technology of UMC (Taiwan). Primarily the ADC unit was designed according to the technical requirements for the readout electronics of the silicon tracking system of the Compressed Baryonic Matter experiment at accelerator facility FAIR (www.gsi.de/en/research/fair.htm). However it can be used for a wider range of applications. To increase accuracy and ensure ADC resolution a rail-to-rail comparator was used. The SAR ADC occupies on chip area of 325μm × 325μm, ENOB is 6.88 bits, maximum DNL less than 0.8 LSB, an INL less than 0.6 LSB, sampling frequency - 20 MHz, clock frequency - 200 MHz, and SNDR is 43.2 dB. With these parameters the ADC consumes about 1.3 mA at a nominal supply voltage of 1.8V.