Title :
Circuit design for a 15-Gb/s Si bipolar decision circuit
Author :
Ishii, K. ; Ichino, H. ; Kobayashi, Y. ; Yamaguchi, C.
Author_Institution :
LSI Lab., NTT, Kanagawa, Japan
Abstract :
The authors have designed and fabricated a high-bit-rate and high-input-sensitivity decision circuit using an advanced super-self-aligned Si bipolar process technology by 0.5-μm photolithography. To realize both a very high bit rate and a high input sensitivity at the same time required not only advanced device technology but also a sophisticated circuit design to extract the maximum performance from the device. The circuit design included optimization of individual transistor sizes to boost the speed and adoption of a wideband preamplifier to enhance the sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mVp-p
Keywords :
bipolar integrated circuits; elemental semiconductors; flip-flops; integrated logic circuits; silicon; 0.5 micron; 15 Gbit/s; Si bipolar process technology; bipolar decision circuit; circuit design; high-bit-rate; high-input-sensitivity; master-slave data flip-flop; photolithography; super-self-aligned; wideband preamplifier; Bit rate; Circuit synthesis; Clocks; Flip-flops; Gallium arsenide; Master-slave; Preamplifiers; Switches; Transistors; Voltage;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-0727-5
DOI :
10.1109/BIPOL.1992.274063
