Title :
Generic linear RC network model for digital CMOS circuits
Author :
Deng, A.C. ; Shiau, Y.C.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
A linear RC delay modeling algorithm is presented to model empirically the timing delays in CMO circuits. The empirical model, an multidimensional function of various circuit and device parameters, is shown to be simplified to a two-dimensional model which estimates the delay of a CMOS gate in terms of the generic RC delay and the rise/fall time of the input transition. Accuracy limitations of the linear RC delay model are discussed, and the empirically generated delay models, based on the generic RC model, are shown to improve the accuracy problem. The model has been installed in an experimental simulator and tested for various circuits. Comparisons are made with SPICE to validate the model´s reliability
Keywords :
CMOS integrated circuits; circuit analysis computing; delays; digital integrated circuits; linear network analysis; CMOS gate delay estimation; SPICE; accuracy limitations; accuracy problem improvement; circuit parameters; device parameters; digital CMOS circuits; empirical timing delay model; empirically generated delay models; experimental simulator; generic linear RC network model; input transition rise/fall time; linear RC delay modeling algorithm; mode reliability; multidimensional function; two-dimensional model; CMOS digital integrated circuits; Circuit simulation; Circuit testing; Computational modeling; Delay effects; Delay estimation; Delay lines; Propagation delay; Semiconductor device modeling; Timing;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100487
