Generic linear RC network model for digital CMOS circuits

A linear RC delay modeling algorithm is presented to model empirically the timing delays in CMO circuits. The empirical model, an multidimensional function of various circuit and device parameters, is shown to be simplified to a two-dimensional model which estimates the delay of a CMOS gate in terms of the generic RC delay and the rise/fall time of the input transition. Accuracy limitations of the linear RC delay model are discussed, and the empirically generated delay models, based on the generic RC model, are shown to improve the accuracy problem. The model has been installed in an experimental simulator and tested for various circuits. Comparisons are made with SPICE to validate the model´s reliability