Title :
Efficient modeling of interconnections in a VLSI circuit
Author :
Nelis, H. ; Dewilde, P. ; Deprettere, E.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
An efficient method is presented for modelling the parasitic capacitance of interconnections in a VLSI circuit. The method is three-dimensional and based on a combination of the Green´s function method and a recently proposed technique for inverting partially specified, positive definite matrices. It yields a reduced yet accurate model and requires O(s) time and O(√s) storage, where s is the size of the layout
Keywords :
Green´s function methods; VLSI; capacitance; circuit layout CAD; Green´s function method; VLSI circuit; efficient interconnection modeling; layout size; matrix inversion; parasitic capacitance; reduced accurate model; three-dimensional method; Computational efficiency; Concurrent computing; Conductors; Equations; Integrated circuit interconnections; Parasitic capacitance; Shape; Sparse matrices; Very large scale integration; Wires;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100490
