High voltage NPN-bipolar transistor using P/sup +/-buried layer in BiCMOS process

Author

Jun-Lin Tsai ; Jei-Feng Huang ; Shih-Hui Chen ; Jeng Gong ; Ruey-Hsin Liou ; Shun-Liang Hsu

Author_Institution

Dept. of Eng., Taiwan Semicond. Manuf. Co. Ltd., Hsinchu, China

fYear

1999

Firstpage

189

Lastpage

192

Abstract

An easy to implement high voltage NPN transistor is integrated in a low voltage (LV) thin (4.5 /spl mu/m) epi-layer BiCMOS process. In this high voltage (HV) bipolar transistor, the conventional N/sup +/-buried layer of the collector is replaced with a P/sup +/-buried layer. The breakdown voltage is higher than 90 V. High current gain (>140), high Early voltage (>500 V), and high frequency response (>1.3 GHz) are also obtained.

Keywords

BiCMOS integrated circuits; power bipolar transistors; semiconductor device breakdown; 1.3 GHz; 4.5 micron; 500 V; 90 V; Early voltage; HV NPN bipolar transistor; LV thin epi-layer BiCMOS process; breakdown voltage; current gain; high frequency response; high voltage bipolar transistor; low voltage BiCMOS process; p/sup +/-buried layer; BiCMOS integrated circuits; Bipolar transistors; Degradation; Doping; Epitaxial layers; Frequency response; Low voltage; Manufacturing processes; Semiconductor device manufacture; Sheet materials;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823876

Filename

823876