Accelerated sensitizable path algorithms for timing verification based on code generation

Author

Claesen, L. ; Schupp, J.P. ; Man, H. De

Author_Institution

IMEC Interuniv. Micro Electron. Center, Leuven, Belgium

fYear

1989

Firstpage

885

Abstract

A method is proposed that is based on a preprocessing of the constrained event graph into an event graph without logical constraints. From the resulting unconstrained event graph, code can be generated that can be evaluated in linear time with respect to the number of event vertices in the graph. The computer implementations of the new algorithms have been tested on real MOS LSI modules and are compared to existing (interpretative) algorithms for false path elimination. Evaluation speedups of up to three orders of magnitude have been achieved for complex time-optimized circuits

Keywords

MOS integrated circuits; circuit analysis computing; delays; large scale integration; logic CAD; accelerated sensitizable path algorithms; code generation; complex time-optimized circuits; computer implementations; constrained event graph preprocessing; evaluation speedups; event vertices; false path elimination algorithms; linear time; logical constraints; real MOS LSI modules; timing verification; unconstrained event graph; Acceleration; Algorithm design and analysis; Circuit simulation; Circuit testing; Delay effects; Delay estimation; Integrated circuit synthesis; Iterative algorithms; Optimization methods; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100493

Filename

100493