Performance analysis of FIR filter using booth multiplier

Finite Impulse Response filters are the most important element in signal processing and communication. FIR filter architecture has multiplier, adder and delay unit. So FIR filter performance is mainly based on multiplier. In this paper presents FIR filter implantation of Booth multiplier using Modified Carry Save Adder (MCSA) and Carry Save Adder (CSA). These techniques are used to improve the performance of delay and Area. The code is written in VHDL and it is simulated in ModelSim 6.3c and synthesis is done in Xilinx ISE 10.1. Finally the design is implemented in Spartan-3 FPGA.