Title :
A six phases LC based ring oscillator for 1.5-3Gbit/s SATA interface
Author :
Tonietto, R. ; Bietti, I. ; Mercier, B. ; Marbot, R. ; Castello, R.
Author_Institution :
Dipt. di Elettronica, Pavia Univ., Italy
Abstract :
A 3 GHz six phases PLL clock synthesizer embedded in a complete Serial Advanced Technology Attachment (SATA) standard compliant oversampling PHY is presented. Multiphase frequency synthesis has been realized using an LC ring structure VCO, featuring improved phase noise and phase accuracy. Integrated in a standard 0.13 μm CMOS process the synthesizer has an active area of 0.8 mm2 and consumes 35 mW while achieving a phase noise of -120dBc/Hz @ 1MHz and a maximum measured phase error of 0.3°. In addition a novel analytical method to investigate the phase accuracy properties of LC ring structures is presented and validated through simulations.
Keywords :
CMOS integrated circuits; integrated circuit noise; jitter; phase locked loops; phase noise; synchronisation; voltage-controlled oscillators; 0.13 micron; 1.5 to 3 Gbit/s; 1.5-3Gbit/s SATA interface; PLL clock synthesizer; VCO; complete Serial Advanced Technology Attachment; multiphase frequency synthesis; phase accuracy; phase noise; six phases LC based ring oscillator; standard compliant oversampling PHY; CMOS process; CMOS technology; Clocks; Frequency synthesizers; Measurement standards; Phase locked loops; Phase noise; Physical layer; Ring oscillators; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346581
