Title :
A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications
Author :
Varzaghani, Aida ; Yang, Chih-Kong Ken
Author_Institution :
Univ. of California, Los Angles, CA, USA
Abstract :
Design of a high-speed low-to-medium resolution analog-to-digital converter with closed-loop pipeline structure has been investigated. We demonstrate a single-path 600MS/s, 5-bit ADC. It is optimally designed to meet the requirements of a serial-link receiver. For high input-bandwidth, total input-capacitance is only 170fF. At high frequencies, to improve resolution beyond the amplifier-settling limit, the reference voltage of each pipeline-stage is digitally tuned. The chip is fabricated in 0.18 μm CMOS technology and consumes 70mW at 1.8V power-supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.18 μm CMOS technology; 0.18 micron; 1.8 V; 5-bit pipelined analog-to-digital converter; 70 mW; closed-loop pipeline structure; serial-link applications; total input-capacitance; Analog-digital conversion; Bandwidth; CMOS technology; Capacitance; Capacitors; Frequency; Pipelines; Sampling methods; Signal resolution; Voltage;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346585
