High efficient modified mixcolumns advanced encryption standard using Vedic multiplier

This paper is designed for the purpose of commercial security algorithms like the Advanced Encryption Standard (AES). We need to protect the sensitive and valuable data transmitted from satellites to ground. It has increased and hence the need to use encryption on board. AES, which is a very popular choice in world communications, is slowly emerging as the preferred option in the aerospace industry includes satellites. In order to meet this requirement, various algorithms have been designed and implemented in the previous, but each of these algorithms have their own shortcomings with respect to an ASIC or an FPGA implementation. In this paper, we propose high efficient architecture for performing the mix columns operation, which is the main function in the Advanced Encryption Standard (AES) method of cryptography. We perform the same using prehistoric Vedic Mathematics techniques. It gives more efficient results in AES. The AES was designed and implemented on a Xilinx Spartan 3 of FPGA. The novel model is designed using Verilog, from which the area and power are measured.