Design of modified vedic multiplier and FPGA implementation in multilevel 2d-DWT for image processing applications

In this paper, the design of Multilevel 2d-DWT with novel Vedic multiplier is presented. In 2d-DWT structure, Digital FIR filter is used to increase the image resolution and eliminate the unwanted noise present in the image. Conventional three level 2d-DWT is designed using regular Vedic multiplier. But it consumes more area and power. And also less image resolution. So MAC unit in the FIR filter is changed to design the efficient FIR filter. Some inputs do not produce the required outputs in conventional MAC units using regular Vedic multiplier. A novel Vedic multiplier with less number of half adders and Full Adders is proposed in order to overcome such an error. Simulation is done in Matlab2008a and Modelsim6.3c. Synthesis and Implementation is performed by Xilinx and FPGA Spartan3.