Design of modified vedic multiplier and FPGA implementation in multilevel 2d-DWT for image processing applications

Author

Kumar, J. Vinoth ; Kumar Charlie Paul, C.

Author_Institution

St. Peter´s Univ., Chennai, India

fYear

2014

fDate

8-8 July 2014

Firstpage

508

Lastpage

511

Abstract

In this paper, the design of Multilevel 2d-DWT with novel Vedic multiplier is presented. In 2d-DWT structure, Digital FIR filter is used to increase the image resolution and eliminate the unwanted noise present in the image. Conventional three level 2d-DWT is designed using regular Vedic multiplier. But it consumes more area and power. And also less image resolution. So MAC unit in the FIR filter is changed to design the efficient FIR filter. Some inputs do not produce the required outputs in conventional MAC units using regular Vedic multiplier. A novel Vedic multiplier with less number of half adders and Full Adders is proposed in order to overcome such an error. Simulation is done in Matlab2008a and Modelsim6.3c. Synthesis and Implementation is performed by Xilinx and FPGA Spartan3.

Keywords

FIR filters; adders; discrete wavelet transforms; field programmable gate arrays; image denoising; image resolution; multiplying circuits; 2d-DWT structure; FPGA Spartan3; MAC unit; Matlab2008a; Modelsim6.3c; Xilinx; digital FIR filter; discrete wavelet transform; full adders; half adders; image processing applications; image resolution; image unwanted noise elimination; modified Vedic multiplier; multilevel 2d-DWT; regular Vedic multiplier; three level 2d-DWT; Adders; Computer architecture; Conferences; Discrete wavelet transforms; Field programmable gate arrays; Finite impulse response filters; 2d-DWT; FIR and FPGA Spartan3; MAC; Vedic Multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Current Trends in Engineering and Technology (ICCTET), 2014 2nd International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-7986-8

Type

conf

DOI

10.1109/ICCTET.2014.6966349

Filename

6966349