Title :
An improved computationally efficient drain current model for double-gate MOSFETs
Author :
Zhou, Xingye ; Zhang, Jian ; Zhou, Zhize ; Zhang, Lining ; Ma, Chenyue ; Wu, Wen ; Zhao, Wei ; Zhang, Xing
Author_Institution :
Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen, China
Abstract :
A drain current model with improved computational efficiency for double-gate (DG) MOSFETs is presented in this paper. Based on our previously proposed potential model, the drain current model is obtained with the implementation of an improved calculation method and the computation efficiency is substantially enhanced. 2-D device simulation (TCAD) is extended to verify the proposed model. In addition, the model is implemented into HSPICE circuit simulator in Verilog-A to prepare for the practical application.
Keywords :
MOSFET; 2D device simulation; Verilog-A; double-gate MOSFET; drain current model; Computational efficiency; Computational modeling; Integrated circuit modeling; Inverters; Logic gates; MOSFETs;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667738
