• DocumentCode
    1639694
  • Title

    Standard testability bus-an applications example

  • Author

    Turino, Jon

  • Author_Institution
    Logical Solutions Technol. Inc., Campbell, CA, USA
  • fYear
    1989
  • Firstpage
    943
  • Abstract
    Summary form only given. The standard testability bus may be implemented in a variety of ways according to the requirements of each specific application. The author describes the application of a standard testability bus to the design of a next-generation automatic test system. The approach selected was protocol independent and could thus support any combination of boundary scannable, VHSIC, and commercially available functional circuitry. The result of the present approach was the ability to meet the system-level testability specifications while at the same time reducing the time and cost associated with design verification, logic and fault simulation, capital equipment cost for external ATE (automatic test equipment), and on-going factory and field testing and troubleshooting
  • Keywords
    VLSI; automatic test equipment; automatic testing; computer interfaces; digital integrated circuits; fault location; logic testing; protocols; standards; VHSIC; automatic test system; boundary scan; cost; design verification; external ATE; factory testing; fault simulation; field testing; production testing; protocol; standard testability bus; system-level testability specifications; time; troubleshooting; Automatic logic units; Automatic testing; Circuit faults; Circuit testing; Costs; Logic design; Logic testing; Protocols; System testing; Very high speed integrated circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
  • Conference_Location
    Washington, DC
  • Type

    conf

  • DOI
    10.1109/TEST.1989.82395
  • Filename
    82395