The implementation of digit-serial FIR filters based on FPGA

Author

Li, Lin ; Lou, Shu-qin ; Liu, Xiaolin ; Liu, Jie

Author_Institution

Sch. of Electron. & Inf. Eng., Beijing Jiaotong Univ.

Volume

1

fYear

2005

Firstpage

419

Abstract

Based on FPGA, a digit-serial FIR filter is implemented. According to the digit-serial algorithm, the digit-serial FIR filter is composed of foundational function modules including the digit-serial adder, the digit-serial multiplier and the delay circuit. Compared with the traditional method, the digit-serial FIR filter based on FPGA exhibits the advantages of high response speed and low hardware consumption. Furthermore, the relationship between the speed and the area is adjusted in a better manner in the digit-serial FIR filter The digit-serial FIR filter with N=2 has the minimum of area-time product

Keywords

FIR filters; adders; field programmable gate arrays; multiplying circuits; FPGA; area-time product; delay circuit; digit-serial FIR filters; digit-serial adder; digit-serial multiplier; foundational function modules; hardware consumption; Adders; Circuits; Clocks; Delay; Digital filters; Field programmable gate arrays; Finite impulse response filter; Hardware; Signal processing algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2005. MAPE 2005. IEEE International Symposium on

Conference_Location

Beijing

Print_ISBN

0-7803-9128-4

Type

conf

DOI

10.1109/MAPE.2005.1617938

Filename

1617938