Title :
Design and verification of Distributed RAM using Look-Up Tables in an SOI-based FPGA
Author :
Han, Xiaowei ; Chen, Stanley L. ; Wu, Lihua ; Zhao, Yan ; Li, Yan
Author_Institution :
Inst. of Semicond., Chinese Acad. of Sci., Beijing, China
Abstract :
A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5μm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement Block RAM in implementing the data storage logic of many applications. The functionality and performance of the Distributed RAM have been proven in our test circuit. Comparing with the published data on the Distributed RAM in Xilinx Spartan FPGA, our Distributed RAM average access time has about 21% improvement.
Keywords :
CMOS logic circuits; field programmable gate arrays; integrated circuit design; random-access storage; silicon-on-insulator; table lookup; SOI-CMOS logic process; SOI-based FPGA; configurable distributed random access memory; data storage logic; distributed RAM; dual-port RAM; logic block; look-up tables; single-port RAM; tile-based FPGA; Arrays; Distributed databases; Field programmable gate arrays; Multiplexing; Random access memory; Table lookup; Timing;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667746
