Communication- and energy-aware mapping on homogeneous NoC architecture with shared memory

With the amount of calculation for wireless and multi-media applications increasing, the Multi-Processor System-on-a-Chip (MPSoC) based on Network-on-Chip (NoC) is used to process massive data in a distributed fashion. Compared with heterogeneous architecture for general embedded low power DSP, homogeneous NoC architecture is much more flexible for dynamical task assignment. In this paper, a new NoC architecture with shared memories on switching nodes is proposed to decrease the communication delay between the Processing Elements (PEs). By breaking PE to PE data transition mode into PE to shared memory to PE mode, the congestion caused by the PE´s concentrated requests is reduced. Experimental results show that about 37.6 transferring cycles and 33.7% power consumption can be reduced applying the same Simulated Annealing (SA) algorithm mapping on the proposed homogeneous NoC.