Design of 250 Mb/s 10-channel CMOS optical receiver array for computer communication

Author

Kim, Kwangoh ; Choi, Jungryoul ; Choi, Joongho

Author_Institution

Dept. of Electr. Eng., Seoul Univ., South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

29

Lastpage

32

Abstract

This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 μm 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for ±2.5 v supply

Keywords

CMOS analogue integrated circuits; integrated optoelectronics; local area networks; optical interconnections; optical phase locked loops; optical receivers; -2.5 to 2.5 V; 0.65 micron; 250 Mbit/s; 330 mW; 70 mW; CMOS optical receiver array; PLL; amplifier chains; computer communication; data recovery; general-purpose CMOS technology; parallel optical interconnection system; phase-locked loop; receiver array; CMOS technology; Optical arrays; Optical computing; Optical design; Optical interconnections; Optical receivers; Optical transmitters; Phase locked loops; Phased arrays; Preamplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824020

Filename

824020