OPNEC-Sim: An efficient simulation tool for Network-on-Chip communication and energy performance analysis

Network-on-Chip (NoC) has been proposed as a paradigm for the network, wireless and multimedia applications executing on embedded chips with massive data processing. It requires high speed data transferring and low power consumption, and then efficient and accurate performance estimation tools are needed for system level optimization and analysis in a flexible way. In this paper, a new NoC simulator OPNEC-Sim is proposed for Multi-Processor-System-on-Chip (MPSoC) simulation, which is capable of accurately simulating the communication and energy performances with a variety of processor, NoC architecture, memory, chip technique and application specific coprocessors. Using the network simulator environment OPNET, C-based simulator could support various NoC architectures, complex mapping, flexible routing algorithms, powerful statics tools and etc.al. By integrating synthesis tools Design Complier (DC), efficient energy consumption simulation can be achieved about 50× faster than that of RTL description. It is able to accurately model NoC mapping performances, allows us to explore the design space rapidly and achieve interesting design implementations.