• DocumentCode
    1640044
  • Title

    50Gb/s 3.3V logic ICs in InP-HBT technology

  • Author

    Van der Wagt, Paul ; Broekaert, Tom ; Yinger, Steve ; Zheng, Sandy ; Srivastava, Nikhil ; Rogers, Jonathan ; Sanders, Jeff ; Thiagarajah, Ramanan ; Coccioli, Roberto ; Arnold, Eric ; Nary, Kevin

  • Author_Institution
    Inphi Corp., Westlake Village, CA, USA
  • fYear
    2004
  • Firstpage
    326
  • Lastpage
    329
  • Abstract
    50Gb/s 3.3V InP-HBT logic ICs with 6ps rise time and 1200mVpp output swing include: D-flip-flop, double-edge triggered flip-flop, dividers, a frequency doubler, XOR/OR gates, and a 1:2 fanout buffer. The DFF has 3pspp deterministic and <190fsrms random jitter, >270deg phase margin, and 12mVpp sensitivity at 40Gb/s and 10-12 BER. The ICs dissipate 480-840mW in 1mm2.
  • Keywords
    CMOS logic circuits; III-V semiconductors; heterojunction bipolar transistors; indium compounds; 3.3 V; 480 to 840 mW; 50 Gbit/s; 6 ps; D-flip-flop; InP-HBT technology; XOR/OR gates; dividers; double-edge triggered flip-flop; fanout buffer; frequency doubler; jitter; logic ICs; Circuit testing; Clocks; Digital integrated circuits; Heterojunction bipolar transistors; Jitter; Latches; Logic; Low voltage; Temperature; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8287-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2004.1346604
  • Filename
    1346604
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1640044