Microprocessor power optimization through multi-performance device insertion

A paradigm shift for multi-performance device insertion from optimizing product-level performance to total power is elucidated. The key limitations of a performance-based insertion methodology are reviewed, where an increase in standby current is sacrificed for an unobservable clock frequency gain. The power optimization, which is based on nodal activity factors and state probabilities, enables a 5% to 8% total power reduction on three mature mega-block designs from two separate 90nm technology generation microprocessors while maintaining constant performance.