A fail-safe microprocessor using dual synthesizable processor cores

Author

Shimamura, Kotaro ; Yamaguchi, Shin Ichiro ; Kanekawa, Nobuyasu ; Miyazaki, Naoto ; Yamada, Hiromichi ; Takahashi, Yoshitaka ; Hirotsu, Teppei ; Tomobe, K. ; Satoh, Kazuyoshi ; Hotta, Takashi ; Fujita, Ryo

Author_Institution

Hitachi Res. Lab., Hitachi Ltd., Ibaraki, Japan

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

46

Lastpage

49

Abstract

A chip level redundant self-checking fail-safe microprocessor has been developed using a 0.35 μm CMOS embedded gate array. The microprocessor integrates two synthesizable processor cores and a self-checking comparator in a single chip. A full-custom processor core was transformed into each of the synthesizable cores for this purpose. Design methodologies suitable for reusing synthesizable processor cores has also been developed. Developed synthesizable processor cores and design methodologies reduce the cost of process migration of the chip. Migrating to the newer process improves the performance of the developed microprocessor with low development cost

Keywords

CMOS digital integrated circuits; application specific integrated circuits; circuit CAD; fault tolerant computing; high level synthesis; integrated circuit design; microprocessor chips; redundancy; 0.35 micron; CMOS embedded gate array; chip level redundancy; design methodologies; dual synthesizable processor cores; fail-safe microprocessor; full-custom processor core; self-checking comparator; self-checking microprocessor; CMOS logic circuits; Central Processing Unit; Control system synthesis; Costs; Design methodology; Laboratories; Microprocessors; Packaging; Random access memory; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824026

Filename

824026