Hardware implementation analysis of SHA-3 candidates algorithms

In order to select a new Standard Hash Algorithm (SHA-3) which supplies more security, a public competition was organized by NIST in 2007. Up to now, 14 candidates have passed the 2nd round. In this paper, we focus on two of these candidate algorithms, namely BLAKE and Shabal. We present the common structure for all the SHA3 candidates. We also design the VLSI circuit and give the hardware evaluations on FPGA and ASIC. Compared with SHA-256 algorithms in the same technology, we found that the SHA3 candidates provide higher throughput but cost more area. Because of raising the complexity of circuit, the efficiency (TP/area) of SHA3 is lower than SHA-256.