Title :
A new lower power Viterbi decoder architecture with glitch reduction
Author :
Ryu, J.H. ; Kim, S.C. ; Cho, J.D. ; Park, H.W. ; Chang, Y.H.
Author_Institution :
Electr. & Comput. Eng., Sung Kyun Kwan Univ., Suwon, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper presents a new algorithm for a lower power Add-Compare-Select (ACS) architecture and glitch minimization for the Viterbi decoder which can reduce the complexity of the computation using HSPICE. Our experimental results show an average 7% reduction in power with the same latency at a cost of 3% increase in area compared with the ACS unit introduced by Tsui et al. (1999)
Keywords :
SPICE; Viterbi decoding; application specific integrated circuits; circuit complexity; circuit optimisation; digital integrated circuits; integrated circuit layout; low-power electronics; 0.65 mum; ACSU butterfly unit; HSPICE; VLSI architecture; add-compare-select architecture; algorithm; computational complexity reduction; glitch minimization; glitch reduction; low power Viterbi decoder architecture; Computer architecture; Convolution; Convolutional codes; Decoding; Delay; Electronic mail; Minimization methods; Signal processing algorithms; Very large scale integration; Viterbi algorithm;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824034
