Title :
A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications
Author :
Sengupta, Aparajita
Author_Institution :
Comput. Sci. & Eng., Indian Inst. of Technol. Indore, Indore, India
Abstract :
This paper introduces a novel methodology for self correction scheme based fast multi criterion exploration and automated architectural synthesis of data dominated applications. The four major novel contributions of the paper are as follows: a) Introduction of two new algorithms that is able to efficiently tackle conditions when the user provided high level constraint values are invalid in nature. This is done using an algorithm to validate the user constraints as well as an algorithm to self rectify the user constraints value automatically if the final Pareto optimal set is found vacant b) Introduction of a novel input format for data flow graph applications and its custom representation c) Introduction of a novel algorithm that is capable to perform automated architectural synthesis using techniques to convert from scheduling to circuit interconnection phase. These new algorithms have been incorporated into a multi criterion design space exploration framework d) New experimental results are reported for the results obtained through proposed multi criterion exploration approach and its speed improvement compared to recent approach. The proposed method, when applied to High Level Synthesis (HLS) benchmarks, yielded speed improvement of more than 90 % compared to recent DSE approach without sacrificing quality of final solution.
Keywords :
Pareto optimisation; data flow graphs; high level synthesis; interconnections; Pareto optimal set; automated architectural synthesis; circuit interconnection phase; data dominated applications; data flow graph applications; high level synthesis benchmarks; multicriterion design space exploration framework; scheduling; self correction scheme based fast multi criterion exploration; user constraint value; Algorithm design and analysis; Clocks; Hardware; Integrated circuit interconnections; Pareto optimization; Power demand; Space exploration; automated architecture synthesis; exploration; multi-criterion; rapid; self correction;
Conference_Titel :
Advances in Computing, Communications and Informatics (ICACCI), 2013 International Conference on
Conference_Location :
Mysore
Print_ISBN :
978-1-4799-2432-5
DOI :
10.1109/ICACCI.2013.6637210