DocumentCode :
1640532
Title :
Charge sharing clock scheme for high efficiency double charge pump circuit
Author :
Huang, Mengshu ; Okamura, Leona ; Yoshihara, Tsutomu
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka, Japan
fYear :
2010
Firstpage :
248
Lastpage :
250
Abstract :
A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional charge pumps.
Keywords :
capacitance; clocks; integrated circuit modelling; charge sharing clock scheme; dynamic power loss; high efficiency double charge pump circuit; parasitic capacitance; Capacitors; Charge pumps; Clocks; Delay; Driver circuits; Generators; Simulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
Type :
conf
DOI :
10.1109/ICSICT.2010.5667772
Filename :
5667772
Link To Document :
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