Implementation of a cycle-based simulator for the design of a processor core

This paper presents an approach to establish and simulate a DSP core by using a cycle-based simulator written in C language. The simulator is written with information of a target DSP core. Instructions are analyzed in order to determine which blocks are used. Then, appropriate control signals are applied to the blocks. The implemented simulator can give the cycle-based information such as changes of control signals and register flags that are not given by instruction-based simulators. After modeling and validating the simulator it is used to verify the HDL model of target DSP core and to enhance its performance as well as to develop applications for the core