Digital background calibration of MDAC stage gain error and DAC error in pipelined ADC

A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined ADC could be replaced by low gain low power counterparts, which results in improving the figure-of-merit (FOM) significantly. A 12-bit 100MS/s pipelined ADC achieves 11.934 bits ENOB and 101.22dB SFDR, compared with 7.685 bits and 50.95dB without calibration.