DocumentCode :
164065
Title :
A new non-volatile memory cell based on the flash architecture for embedded low energy applications: ATW (Asymmetrical Tunnel Window)
Author :
Bartoli, J. ; Della Marca, V. ; Delalleau, J. ; Regnier, A. ; Niel, S. ; La Rosa, F. ; Postel-Pellerin, J. ; Lalande, F.
Author_Institution :
ST-Microelectron., Rousset, France
fYear :
2014
fDate :
13-15 Oct. 2014
Firstpage :
117
Lastpage :
120
Abstract :
In this paper we propose a new non-volatile charge trap memory architecture implemented on 200mm wafer in 90nm technology node. The aim of this work is to investigate an alternative and scalable solution for embedded low energy applications. The Asymmetrical Tunnel Window (ATW) memory cell has been developed in order to improve the programming operation during a hot carrier injection. The main property of this device is the presence of an asymmetrical tunnel oxide thickness along the channel. This characteristics enables an improvement in terms of current consumption and injection efficiency with respect to the standard Flash floating gate memory cell. In this work we describe the fabrication process of ATW memory cell and, using a commercial TCAD simulator and experimental results, we demonstrate the good functioning of our device thanks to the increased control gate/floating gate (CG/FG) coupling factor. To conclude we confirm the reliability performances with the endurance experiments up to 100k cycles.
Keywords :
CMOS memory circuits; flash memories; hot carriers; integrated circuit reliability; technology CAD (electronics); tunnelling; ATW memory cell; CG-FG coupling factor; asymmetrical tunnel oxide thickness; asymmetrical tunnel window memory cell; commercial TCAD simulator; compatible CMOS fabrication process; control gate-floating gate coupling factor; current consumption; embedded low energy application; hot carrier injection; injection efficiency; non-volatile charge trap memory cell architecture; reliability; size 200 mm; size 90 nm; standard flash floating gate memory cell; Computer architecture; Couplings; Logic gates; Microprocessors; Nonvolatile memory; Programming; Standards; TCAD simulation; asymmetrical oxide thicknesses; endurance; low energy; non-volatile memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Conference (CAS), 2014 International
Conference_Location :
Sinaia
ISSN :
1545-827X
Print_ISBN :
978-1-4799-3916-9
Type :
conf
DOI :
10.1109/SMICND.2014.6966409
Filename :
6966409
Link To Document :
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