Design and VLSI implementation of high performance NCO based on Galois fields

In this paper, a novel NCO architecture is presented. The error-free computational property of Galois fields is used to improve the NCO performance, which is commonly restricted by the phase truncation effect in the traditional sine look-up table based architecture. Compared with the conventional digital oscillator, the frequency switching time of our design is reduced largely, which makes it attractive candidate for applications that require fast and phase-continuous frequency switching. The SFDR of the architecture is 75 dB with 10-bit phase resolution and 12-bit amplitude resolution. The Verilog RTL is simulated and verified to work at 240 MHz in a 2V3000FG676-6 Xilinx Virtex2 FPGA.