A VLSI implementation of MPEG-2 AAC decoder system

Author

Lee, Keun-Sup ; Jeong, Nam-Hun ; Bang, Kyoung-Ho ; Youn, Dae-Hee

Author_Institution

Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

139

Lastpage

142

Abstract

This paper presents a real-time MPEG-2 AAC decoding system, which can decode 2-channel main profile MPEG-2 AAC bitstream. The system consists of a simple fixed-point programmable DSP core and two hardwired logic modules, which perform Huffman decoding and prediction respectively. To verify the designed decoding system, simulator model has been developed based on C-language. For the verification of decoding algorithm, the 16-bit PCM output of the system was compared with the result of the floating-point simulation, and the result showed the maximum of 2-bit difference. For the verification of real-time decoding, the number of the clock cycles in the worst simulation case was compared with that of the required clock cycles for the real-time decoding, and the result verified the real-time decoding of designed system

Keywords

VLSI; decoding; digital signal processing chips; real-time systems; 16 bit; C-language model; Huffman decoding; PCM output; VLSI; decoding algorithm; fixed-point programmable DSP core; floating-point simulation; hard-wired logic module; prediction technique; real-time MPEG-2 AAC decoding system; Clocks; Decoding; Digital signal processing; Filter bank; Huffman coding; IEC standards; ISO standards; Logic; Real time systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824047

Filename

824047