Optimising variability tolerant standard cell libraries

This paper describes an approach to optimise transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant to the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced SPICE models based on 3D-atomistic simulations, a genetic algorithm optimises the device widths within a circuit using a multi-objective fitness function. The results show the impact of threshold voltage variation can be reduced by optimising transistor widths, and suggest a similar method could be extended to the optimisation of larger circuits.