A novel zero overhead obfuscation technique for securing FPGA designs

With the expansion of the use of reconfigurable logic circuits beyond commercial markets to avionic and military applications, designs in FPGA takes on the additional aspects of safety and national security. JTAG is a well-known standard mechanism in reconfigurable devices by allowing in-system design updates and debugging. Although it provides high controllability and observability, it also poses grave security challenges because of its read back and reprogramability features. The designer needs an effective tamper resistance mechanism to protect the intellectual property and sensitive data that might exist in a JTAG compliant FPGA based hardware system. In this paper, the main post-configuration vulnerabilities of FPGAs through JTAG are identified and preventive obfuscation models to guarantee secure platforms are proposed. The proposed obfuscation circuitry provides robust security features to overcome and prevent reverse engineering and unauthorized operation of the JTAG port, while occupying almost zero overhead.