Title :
VLSI architecture for low power motion estimation using high data access reuse
Author :
Kim, Bo-Sung ; Cho, Jun-dong
Author_Institution :
VLSI Algorithmic Design Autom. Lab., SungKyunKwan Univ., Kyunggi-do, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper presents a new VLSI architecture of the motion estimation in MPEG-2. Previously various full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have inefficiently a large number of external memory access. Our new architecture efficiently reuses data to decrease external memory accesses and saves the computational time by using a parallel algorithm
Keywords :
VLSI; data compression; digital signal processing chips; image coding; low-power electronics; motion estimation; parallel algorithms; parallel architectures; DSP chip; MPEG-2; VLSI architecture; external memory accesses reduction; high data access reuse; low power motion estimation; parallel algorithm; Computer architecture; Concurrent computing; Cost function; Design automation; Hardware; Motion estimation; Parallel algorithms; Systolic arrays; TV; Very large scale integration;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824053
