Title :
A 12 bit current-mode folding/interpolation CMOS A/D converter with 2 step architecture
Author :
Kim, Hyung Hoon ; Yoon, Kwang Sub
Author_Institution :
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
An 12 bit 20 MS/s current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease the power dissipation within the ADC. The proposed ADC is implemented by a 0.65 μm n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ±0.5 LSB, an integral nonlinearity (INL) of ±1.0 LSB, the power dissipation of 280 mW with a power supply of 5 V
Keywords :
CMOS integrated circuits; analogue-digital conversion; current-mode circuits; interpolation; low-power electronics; 0.65 micron; 12 bit; 280 mW; 5 V; CMOS A/D converter; DNL; INL; analog to digital converter; current-mode operation; differential nonlinearity; folding/interpolation ADC; integral nonlinearity; multiplied folding amplifiers; n-well CMOS single poly/double metal process; power dissipation reduction; two-step flash architecture; Analog-digital conversion; CMOS process; Circuits; Interpolation; Power amplifiers; Power dissipation; Power supplies; Signal generators; Signal processing; Voltage;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824056
