Author_Institution :
Electron. & Commun. Eng. Dept., Bharati Vidyapeeth´s Coll. of Eng., New Delhi, India
Abstract :
One of the major concerns for designing VLSI circuits has been the amount of power dissipated by these circuits. Hence, adiabatic techniques such as ECRL and PFAL for low power circuit design came into being. This paper proposes design of basic gates using these two techniques. Tanner ECAD tool is used and the circuits are implemented using the 1.25 micron technology. Transistor count for AND, NOR, XOR for ECRL and PFAL are 6, 6, 10 and 8, 8, 12 respectively. Average power consumed in microwatts for AND, NOR, XOR gates using ECRL and PFAL are observed to be 6.915985, 7.007541,12.87065 and 13.58256,13.46340, 20.21517 respectively. Maximum frequency in Mega Hertz for which distortion less output was obtained for AND, NOR, XOR gates using ECRL and PFAL is 100, 200, 150 and 150, 250, 100 respectively. The corresponding average power values in microwatts for this frequency are 15.46638, 20.33593, 28.74033 and 124.2305, 59.36848, 28.92239 respectively. Maximum load capacitance for ECRL and PFAL for AND, NOR, XOR is 0.1, 0.03, 0.02 and 0.2, 0.09, 0.04 respectively.
Keywords :
VLSI; integrated circuit design; logic CAD; logic gates; AND gates; ECRL technique; NOR gates; PFAL technique; Tanner ECAD tool; VLSI circuits design; XOR gates; basic gates design; efficient charge recovery logic; frequency 100 MHz; frequency 150 MHz; frequency 200 MHz; frequency 250 MHz; low power circuit design; positive feedback adiabatic logic; power 124.2305 muW; power 15.46638 muW; power 20.33593 muW; power 28.74033 muW; power 28.92239 muW; power 59.36848 muW; power dissipation; size 1.25 mum; transistor count; Conferences; Informatics; ECAD; ECRL; PAL; PFAL; SCRL; Tanner;
