A 12-Bit 125MSPS ADC with capacitor mismatch trimming

In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12-bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, a high performance sample-and-hold amplifier (SHA) front end, and 7 pipelined sub-ADC stages. A double poly triple metal 0.35 μm BiCMOS process with 5V analog power supply is used in the design. This ADC achieves an SNR of 66 dB and an SFDR of 80 dB for sampling analog input frequencies up to 50 MHz.