An 8Mb demonstrator for high-density 1.8V Phase-Change Memories

Author

Bedeschi, F. ; Resta, C. ; Khouri, O. ; Buda, E. ; Costa, L. ; Ferraro, M. ; Pellizzer, F. ; Ottogalli, F. ; Pirovano, A. ; Tosi, M. ; Bez, R. ; Gastaldi, R. ; Casagrande, G.

Author_Institution

MPG & Central R&D, STMicroelectronics, Agrate Brianza, Italy

fYear

2004

Firstpage

442

Lastpage

445

Abstract

An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 μm² Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 μm CMOS technology is presented. Realistically large 4Mb tiles with a voltage regulation scheme that allows fast bitline precharge and sense are proposed. An innovative approach that minimizes the array leakage has been used to verify the feasibility of high-density PCM memories with improved Read/Write performance compared to Flash. Finally, cells distributions and first endurance measurements demonstrate the chip functionality and a good working window.

Keywords

CMOS memory circuits; bipolar transistors; phase changing circuits; 1.8 V; 3 V; 3V 0.18 μm CMOS technology; 8 Mbit; 8Mb demonstrator; BJT; cells distributions; chip functionality; endurance measurements; fast bitline precharge; high-density 1.8V Phase-Change Memories; voltage regulation scheme; CMOS process; CMOS technology; Nonvolatile memory; Phase change materials; Phase change memory; Phased arrays; Read-write memory; Throughput; Tiles; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8287-0

Type

conf

DOI

10.1109/VLSIC.2004.1346644

Filename

1346644