Title :
Test and design for testability of reconvergent fan-out CMOS logic networks
Author :
Darlay, F. ; Courtois, B.
Author_Institution :
IMAG/TIM3 Lab., Grenoble, France
Abstract :
The authors address the robustness of adjacent vector sequences in irredundant RFO (reconvergent fan-out) logic networks made up of primitive CMOS (NAND, NOR) and fully complemented MOS (FCMOS) gates. RFO structures in which these sequences are robust are defined, and a DFT (design-for-testability) method for solving the remaining problems is described. It is shown that a large percentage of stuck-open faults are detected by adjacent vector sequences. The robustness of the sequences is guaranteed in many cases
Keywords :
CMOS integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic design; logic testing; adjacent vector sequences; design for testability; fully complemented MOS gates; logic design; primitive CMOS gates; reconvergent fan-out CMOS logic networks; robustness; stuck-open faults; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Design for testability; Fault detection; Hazards; Logic design; Logic testing; Robustness;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82406
