Scalable latency tolerant architecture (SCALT) and its evaluation

Author

Shimizu, Naohiko ; Mitake, Daisuke

Author_Institution

Fac. of Eng., Toukai Univ., Kanagawa, Japan

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

221

Lastpage

224

Abstract

The deviation of the memory latency is hard to be predicted for in software, especially on the SMP or NUMA systems. As a hardware correspondent method, the multi-thread processor has been devised. However, it is difficult to improve the processor performance with a single program. We have proposed SCALT that uses a buffer in a software context. For the deviation of a latency problem, we have proposed a instruction to check the data arrival existence in a buffer. This paper describes the SCALT, which uses a buffer check instruction, and its performance evaluation results, obtained analyzing the SMP system through event-driven simulation

Keywords

buffer storage; computer architecture; fault tolerant computing; performance evaluation; NUMA system; SCALT; SMP system; buffer check instruction; event-driven simulation; memory latency; multi-thread processor; performance evaluation; processor performance; scalable latency tolerant architecture; Buffer storage; Computer architecture; Delay; Hardware; Logic; Out of order; Prefetching; Proposals; Software maintenance; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824068

Filename

824068